The present invention relates to a channel switching system and, more particularly, to a channel switching system applicable to a digital radio communication system for switching a regular radio channel and a standby channel as needed.
A large capacity radio communication system customarily includes a standby radio channel in addition to regular radio channels to provide for circuit downs due to channel maintenance, fading, equipment failures and other occurrences. When a certain regular channel fails, a transmitting side connects a signal being transmitted over that regular channel to the standby channel in parallel with the regular channel while a receiving side switches the signal coming in over the regular channel to the signal coming in over the standby channel. The regular and standby channels are different from each other with respect to propagation delay and, moreover, this propagation delay is dependent upon fading and other factors. Hence, in the case that the signal to be transmitted is a data signal, the two data signals transmitted over the regular and standby channels are not always coincident with respect to timing. It follows that although a permanent component of the propagation delay difference may be compensated for beforehand, an increase in a fluctuating component beyond one clock period of the data signal brings about a bit error during channel switching at the receiving side.
To eliminate such bit errors, use is generally made of a channel switching system of the type switching the channel after setting up a bit period between the two transmitted data signals. A channel switching system with this kind of periodic switching function includes a transmit signal processing circuit for converting the speed of a data signal to be transmitted at a high speed. The resulting converted signal is fed to a modulator associated with a regular channel after frame sync bits, parity bits, check bits and other extra bits have been added to the signal. Prior to channel switching, an output data signal of a transmit signal processing circuit associated with a regular channel to be switched is connected in parallel to a modulator associated with a standby channel by a switching circuit which is installed in a transmitting terminal. A standby channel usually sends a test pattern while it is in a standby condition. A transmit signal processing circuit associated with the standby channel and adapted to insert extra bits in the test pattern is operated asynchronously with the transmit signal processing circuit of the regular channel, so that the clock of the data signal arriving at the modulator on the standby channel at the instant of parallel connection which occurs at the switching circuit of the transmitting side fluctuates. Any discontinuous fluctuation of the clock is apt to bring the modulator out of synchronism, resulting in a need for a substantial recovery time. In the light of this, the switching circuit at the transmitting side produces its own clock synchronous to the clock of an incoming data signal by using a phase locked loop and retimes the data signal with the own clock, thereby freeing the clock of an output data signal from discontinuous fluctuations.
The two signals sent over the regular and standby channels are individually demodulated by exclusive demodulators to become data signals. The two data signals each includes frame sync bits which have been inserted by the transmit signal processing circuit associated with the regular channel. A switching circuit at the receiving side causes the bits of the two data signals into coincidence by using the timing of a frame sync bit, thereby switching the channels without any bit error. The demodulator includes a phase locked loop for recovering a clock from an incoming modulated signal. By the parallel connection effected by the switching circuit at the transmitting side, the clock of the modulated signal inputted to the demodulator is changed also. Should the response speed of the phase locked loop of the demodulator be lower than the response speed of the phase locked loop of the switching circuit at the transmitting side (i.e. should the band width Bd of the former be narrower than the band width Bs of the latter), the phase locked loop of the demodulator would fail to follow the variation of the clock of the modulated signal. The result is the step-out which needs a substantial period of time to be recovered. Hence, the band width Bd has to be maintained greater than the band width Bs.
An increase in the band width Bd of the phase locked loop adapted for clock recovery lowers the carrier-to-noise (C/N) ratio of the recovered clock and thereby aggravates the bit error rate of the modulator. This is especially true when use is made of a multi-level modulation system such as a multi-level quadrature amplitude modulation (QAM) system. However, the band width Bd cannot be reduced to a sufficient degree without causing the pull-out of the demodualtor in the event of channel switching and therefore without increasing the channel switching time.
As discussed above, a dilemmatic situation with the prior art channel switching system is that the bit error rate of a modulator cannot be reduced without increasing the channel switching time.
The above-mentioned prior art is disclosed in, for example, U.S. Pat. Nos. 4,442,518 and 4,686,675.